Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2011-04-05
2011-04-05
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C712S222000, C712S226000
Reexamination Certificate
active
07921278
ABSTRACT:
An “early exit” of an iterative refinement algorithm is implemented by effectively disabling read after write dependency stalls of newer instructions, as well as disabling the register write enable of these instructions, for the remainder of the algorithm, in addition to disabling the register write enable of these instructions. By doing so, the latency of the algorithm is reduced and the performance is increased without the complexity and potential poor performance of compare and branch instructions that might otherwise be required.
REFERENCES:
patent: 3577190 (1971-05-01), Cocke et al.
patent: 5303355 (1994-04-01), Gergen et al.
patent: 5832258 (1998-11-01), Kiuchi et al.
patent: 6079008 (2000-06-01), Clery, III
Muff Adam James
Tubbs Matthew Ray
Chan Eddie P
International Business Machines - Corporation
Partridge William B
Wood Herron & Evans LLP
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