Digital signal processor computation core with pipeline...

Details Digital signal processor computation core with pipeline... Digital signal processor computation core with pipeline...

2005-02-22

2005-02-22

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

C712S219000

Reexamination Certificate

active

06859872

ABSTRACT:
A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.

REFERENCES:
patent: 4777591 (1988-10-01), Chang et al.
patent: 4777612 (1988-10-01), Tomimitsu
patent: 5043868 (1991-08-01), Kitamura et al.
patent: 5258939 (1993-11-01), Johnstone et al.
patent: 5282155 (1994-01-01), Jones
patent: 5297069 (1994-03-01), Asato et al.
patent: 5297071 (1994-03-01), Sugino
patent: 5343404 (1994-08-01), Girgis
patent: 5428741 (1995-06-01), Ho et al.
patent: 5502747 (1996-03-01), McGrath
patent: 5517436 (1996-05-01), Andreas et al.
patent: 5532938 (1996-07-01), Kondo et al.
patent: 5588118 (1996-12-01), Mandava et al.
patent: 5590352 (1996-12-01), Zuraski, Jr. et al.
patent: 5613152 (1997-03-01), VanMeerbergen et al.
patent: 5642382 (1997-06-01), Juan
patent: 5680335 (1997-10-01), Ikeyama et al.
patent: 5710914 (1998-01-01), Verbauwhede et al.
patent: 5748515 (1998-05-01), Glass et al.
patent: 5764553 (1998-06-01), Hong
patent: 5787025 (1998-07-01), Muwafi et al.
patent: 5787026 (1998-07-01), Orenstein et al.
patent: 5790826 (1998-08-01), Thusoo et al.
patent: 5839108 (1998-11-01), Daberko et al.
patent: 5867726 (1999-02-01), Ohsuga et al.
patent: 5896543 (1999-04-01), Garde
patent: 5926644 (1999-07-01), Hays
patent: 5941940 (1999-08-01), Prasad et al.
patent: 5987490 (1999-11-01), Alidina et al.
patent: 6058408 (2000-05-01), Fischer et al.
patent: 6078941 (2000-06-01), Jiang et al.
patent: 6092184 (2000-07-01), Wechsler
patent: 6119217 (2000-09-01), Suzuoki
patent: 6167497 (2000-12-01), Nakatsuka et al.
patent: 6175370 (2001-01-01), Kunimatsu
patent: 6175912 (2001-01-01), Alidina et al.
patent: 6230180 (2001-05-01), Mohamed
patent: 6230238 (2001-05-01), Langan et al.
patent: 6230257 (2001-05-01), Roussel et al.
patent: 6247036 (2001-06-01), Landers et al.
patent: 6260137 (2001-07-01), Fleck et al.
patent: 6266807 (2001-07-01), McGarity et al.
patent: 6292886 (2001-09-01), Makineni et al.
patent: 6321327 (2001-11-01), Makineni et al.
patent: 6327690 (2001-12-01), Zhang et al.
patent: 6349382 (2002-02-01), Feiste et al.
patent: 6425070 (2002-07-01), Zou et al.
patent: 6496705 (2002-12-01), Ng et al.
patent: 6532273 (2003-03-01), Mobin et al.
patent: 6532530 (2003-03-01), Kim et al.
patent: 20020002574 (2002-01-01), Jennings, III
patent: 20020041658 (2002-04-01), Henderson et al.
patent: 20020152250 (2002-10-01), Staszewski
patent: 20030009659 (2003-01-01), DiSanto et al.
patent: 20030028743 (2003-02-01), Catherwood et al.
patent: 0 425 410 (1991-05-01), None
patent: 0 580 924 (1994-02-01), None
patent: 0 741 358 (1996-11-01), None
patent: 0 789 297 (1997-08-01), None
patent: 0 901 068 (1999-03-01), None
patent: WO 9914663 (1999-03-01), None
Hennessy and Patterson, Computer Architecture—A Quantitative Approach, 2nd Edition, 1996, pp. 129-130, 132, 153, 189-190, and 201-202.*
Patterson, D.A., CS152 Computer Architecture and Engineering—Midterm II, University of California, Berkley, Oct. 19, 1997, pp. 11-15.*
Hennessy and Patterson, “Computer Architecture—A Quantitative Approach, 2nd Edition,” 1996, pp. 127-128.*
Conte, T.M., “Challenges to Combining General-Purpose and Multimedia Processors”, Computer, US, IEEE Computer Society, Long Beach, CA, vol. 30, No. 12, Dec., 1997, pp. 33-37.
Ernst, R. “Long Pipelines in Single-Chip Digital Signal Processors—Concepts and Case Study”, IEEE Transactions on Circuits and Systems, New York, vol. 38, No. 1, 1991, pp. 100-108.
Wakerly, John F., “Digital Design, Principles and Practice”, Prentice Hall, 3rdEdition, pp. 230-240.

Affiliated with

Also associated with

Rating

Digital signal processor computation core with pipeline... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital signal processor computation core with pipeline..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital signal processor computation core with pipeline... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3510764