Dynamic instruction dependency monitor and control system

Details Dynamic instruction dependency monitor and control system Dynamic instruction dependency monitor and control system

2008-09-30

2008-09-30

Dollinger, Tonia L. M. (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Scoreboarding, reservation station, or aliasing

Reexamination Certificate

active

10616647

ABSTRACT:
Method and system for controlling the dynamic latency of an arithmetic logic unit (ALU). In one embodiment, the identification of the destination operand of an instruction is stored in a temporary register ID/thread control ID pair pipeline if the destination operand is a temporary register. Furthermore, each source operand of an instruction is checked against the identifications stored in a group of temporary register ID/thread control ID pipelines. If a source operand is matched to an identification stored in the temporary register ID/thread control ID pipelines, the ALU does not execute the instruction until the matched identification is no longer matched in the pipelines.

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FOLDOC; pipeline definition; 1996.
Hirata et al.; “An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads”; 1992; ACM.

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