Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2005-12-27
2005-12-27
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
C712S034000, C712S234000
Reexamination Certificate
active
06981131
ABSTRACT:
The present invention provides a data processing apparatus and method for evaluating condition codes comprising a pipelined processor operable to execute a sequence of instructions, a set of condition codes being maintained by the processor, and the state of the condition codes being set by execution of condition code setting instructions in the sequence. The sequence of instructions further includes conditional instructions that are conditionally executed depending on the state of a number of those condition codes, with the pipelined processor comprising a plurality of pipeline stages including a predetermined pipeline stage at which the state of the condition codes are set by the condition code setting instructions. Condition code evaluation logic is associated with the predetermined pipeline stage and is operable, when one of the conditional instructions is in the predetermined pipeline stage, to evaluate the state of the number of the condition codes in order to generate a pass signal indicating whether the conditional instruction is to be executed. Additional condition code evaluation logic is associated with a preceding pipeline stage, and is operable, when one of the conditional instructions is in that preceding pipeline stage, to evaluate the state of the number of the condition codes in order to generate an additional pass signal. Condition code setting instruction determination logic is operable to determine whether there is a condition code setting instruction in either the predetermined pipeline stage or any pipeline stages between said preceding pipeline stage and the predetermined pipeline stage.
REFERENCES:
patent: 5317703 (1994-05-01), Hiraoka et al.
patent: 5408620 (1995-04-01), Asakawa et al.
patent: 5471593 (1995-11-01), Branigin
patent: 5600848 (1997-02-01), Sproull et al.
ARM Limited
Kim Kenneth S.
Nixon & Vanderhye P.C.
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