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Early condition code evaluation at pipeline stages...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Early data return indication mechanism

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Early data return indication mechanism for data cache to...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Early exit processing of iterative refinement algorithm...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Early exit processing of iterative refinement algorithm...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Efficient read after write bypass

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Electronic processor providing direct data transfer between...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Electronic system and method for maintaining synchronization of

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Elimination of potential renaming stalls due to use of...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Emit vector optimization of a trace

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Enhanced virtual renaming scheme and deadlock prevention...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Error recovery following speculative execution with an...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Event counter

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Execution displacement read-write alias prediction

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Execution of data processing instructions

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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