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Drive preparation methods for intelligent backup systems

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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DSP architecture optimized for memory accesses

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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DSP code swapping with continuous DSP execution

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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DSP with distributed RAM structure

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Dual active bank memory controller

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Dual apparatus and method thereof using concurrent write...

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Dual associative-cache directories allowing simultaneous read op

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual axis RAID systems for enhanced bandwidth and reliability

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Dual bus computer network using dual busses with dual spy module

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual bus data storage system having an addressable memory with t

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Dual bus memory transactions using address bus for data transfer

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual bus network cache controller system having rapid invalidati

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual bus system with multiple processors having data coherency m

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual cache directories with respective queue independently execu

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual cache module support for array controller

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual cache with multiple interconnection operation modes

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual comparator scheme for detecting a wrap-around condition and

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual controller system for dynamically allocating control of...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Dual controller system for dynamically allocating control of...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
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Dual edge command

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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