Dual bus network cache controller system having rapid invalidati

Details Dual bus network cache controller system having rapid invalidati Dual bus network cache controller system having rapid invalidati

1997-03-11

1998-12-01

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711130, 711133, 711142, 711143, 711146, 711149, G06F 1208

Patent

active

058453245

ABSTRACT:
A computer architecture where a processor with store-through cache is linked with a cache control module, a bus interface to dual system busses, a system spy module monitoring the dual system busses for new data overwrites and an invalidation queue for holding cache addresses to be invalidated while the entire network is controlled by a programmable state machine system for enabling cache access and cache invalidation operations.

REFERENCES:
patent: 5157774 (1992-10-01), Culley
patent: 5446863 (1995-08-01), Stevens et al.
patent: 5524235 (1996-06-01), Larson et al.

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