Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-07-28
2009-06-16
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S211000, C711S154000, C365S189020, C365S189030, C365S230020
Reexamination Certificate
active
07549033
ABSTRACT:
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.
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Choi Joo S.
Keeth Brent
Manning Troy A.
Bataille Pierre-Michel
Krofcheck Michael C
Micro)n Technology, Inc.
Schwegman Lundberg & Woessner, P.A.
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