Dual associative-cache directories allowing simultaneous read op

Details Dual associative-cache directories allowing simultaneous read op Dual associative-cache directories allowing simultaneous read op

1997-04-14

2000-02-08

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711124, 711119, 711113, G06F 1200

Patent

active

060237465

ABSTRACT:
A method of accessing values stored in a cache used by a processor of a computer system, whereby two read operations may occur simultaneously is disclosed. Memory blocks from a memory device are loaded into respective cache lines of the cache, and address tags associated with the memory blocks are written into two redundant cache directories of the cache. Thereafter, a first memory block can be read from the cache using the first cache directory, while a second memory block is simultaneously read from the cache using the second cache directory. The cache can have a single cache entry array, or two (redundant) cache entry arrays connected respectively to the two cache directories. If an error occurs when examining a particular address tag in one cache directory, then a redundant address tag can be substituted for the particular address tag by examining a corresponding line of the other cache directory.

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patent: 5319766 (1994-06-01), Thaller et al.
patent: 5325520 (1994-06-01), Nguyen et al.
patent: 5502728 (1996-03-01), Smith, III

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