Dual cache directories with respective queue independently execu

Details Dual cache directories with respective queue independently execu Dual cache directories with respective queue independently execu

1997-04-14

2000-07-04

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711124, 711119, 711113, G06F 1200

Patent

active

060852887

ABSTRACT:
A method of storing values in a cache used by a processor of a computer system, the cache having two or more cache directories. An address tag associated with the memory block is written into a first cache directory during an initial processor cycle, the address tag is written into a second cache directory during the next or subsequent processor cycle. Another address tag associated with a different memory block may be read from the second cache directory during the initial processor cycle. Additionally, another address tag associated with yet a different memory block may be read from the first cache directory during the subsequent processor cycle. A write operation for the address tag may be placed into a write queue of the first cache directory, prior to writing the address tag into the first cache directory, and the same write operation may be placed into a write queue of the second cache directory, prior to said step of writing the address tag into the second cache directory; the write queue of the second cache directory executes its contents independently of the write queue of the first cache directory. This staggered writing ability imparts greater flexibility in carrying out write operations for a cache having multiple directories, thereby increasing performance.

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