Dual active bank memory controller

Details Dual active bank memory controller Dual active bank memory controller

2003-08-01

2008-03-11

Sough, Hyung S. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S111000, C711S113000, C711S114000, C711S130000, C711S162000, C711S154000, C711S158000, C711S160000, C711S167000, C711S168000, C711S104000, C711S105000, C711S005000, C711S106000, C711S163000, C709S213000

Reexamination Certificate

active

07343457

ABSTRACT:
A memory controller for managing memory requests from a plurality of requesters to a plurality of memory banks is disclosed. The memory controller includes an arbiter, a first path controller, a second path controller, and a synchronizer. The arbiter is configured to receive the memory requests from the plurality of requesters and identify requests for processing responsive to the requested memory banks. The first and second path controllers are coupled to the arbiter and the plurality of memory banks with the first path controller configured to process the first memory request and the second path controller configured to process the second memory request. The synchronizer is coupled between the first path controller and the second path controller for synchronizing the first and second path controllers such that the first and second memory requests processed by the first and second path controllers, respectively, do not conflict.

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