Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2002-08-16
2004-09-14
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S003000, C711S005000, C711S115000, C714S005110
Reexamination Certificate
active
06792511
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to an array controller for use in a fault tolerant hard drive-based data storage system, and, more particularly, for managing and supporting up to two detachable cache modules in the array controller, making sure that the data is not lost because of user mishandling of the cache modules.
An array controller that allows one or two easily detachable cache modules to be plugged in also creates a potential problem of users mishandling the cache boards while there is good data in them. A user can swap the cache modules while plugging them in another controller, or can mix and match with another controller's cache modules while there is good data in them. This can cause the system to be corrupted if not detected and handled properly.
The use of two cache boards in an array controller increases cache capacity and performance. However this increase in capacity and performance comes at the price of potential mishandling by the end user. The user might cause the controller firmware to encounter anomalous or lock-up conditions due to the mishandling of the cache boards while, for example, moving them from one controller to another.
It would therefore be desirable for the controller to be able to detect and if possible correct for these anomalous situations and to avoid erasing good data in the cache boards, creating a system lock-up, or creating another undesirable fault condition.
SUMMARY OF THE INVENTION
According to the present invention, an external array controller based on Power PC processor includes two cache boards. The controller memory consists of 2 MB of ROM to hold firmware image and 16 MB of RAM as main memory. The controller also includes a local PCI bus, also called secondary PCI bus. All the PCI devices are connected to each other through this bus. Out of 16 MB, the lower 8 MB of RAM is only visible to Power PC and is used for code and local data. The upper 8 MB is visible on local PCI bus and is available for access to all the devices on the bus. The local PCI devices also include a bridge between Power PC and local PCI bus, two dual-channel SCSI controllers, each with two SCSI buses, and a Fiber Channel controller. The controller enclosure box also has a PCI bus, called Primary PCI bus and two controller slots connected through this bus. The controller has a bridge between the secondary PCI bus and the primary PCI bus. The bridge also serves as a DMA engine. It also has provision for attaching up to two DIMMs (memory modules). The bridge is capable of DMAing (transferring data) from secondary PCI bus or its memory to primary PCI bus.
The bridge memory (DIMMs) is used for the controller cache. Thus, the terms “DIMMs” and “cache boards” are used interchangeably. The DIMMs are equipped with batteries in order to preserve data if power or the controller fails while there is cached data in the DIMMs. The firmware is implemented so that it caches data at the logical volume level and not at the physical drives level. The entire logical volume is viewed as divided into logical volume stripes, each being 32 sectors long. Similarly, the cache is also viewed as divided into cache lines, each line being 32 sectors in length. A given stripe is mapped on to a cache line using set associative mapping. There are algorithms to handle conflicts, that is, if a stripe is mapped on to an already occupied cache line. The unit of cache accesses is a sector (512 bytes), that is, cache can only be accessed in terms of sectors.
The controller cache is also referred to as Array Accelerator. As the name suggests, it provides a big boost to the controller performance. The function of having controller cache between host and disk drives is much similar to having processor cache between the processor and main memory in a computer system. For example, for a write operation initiated from a host, the controller can cache the incoming data and immediately send back completions to the host without actually writing data to disk. The data is later flushed to the drives when the controller is free enough. This way its performance increases by many folds. Such a write operation is referred to as a “Posted Write”. Similarly, if the controller observes a pattern in read operations initiated by the host, it can read more data from the drives then needed into the cache, so that later on when host needs the data, it is readily available from cache.
The array controller of the present invention also includes software to enable the controller to determine whether or not there is any unflushed data in a cache board, to identify a used cache board, and to detect whether or not the cache board belongs to the controller in use or to another controller. Once a problem is identified, the controller is further programmed to issue an appropriate message and to take corrective action, if possible.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention, which proceeds with reference to the accompanying drawings.
REFERENCES:
patent: 5448719 (1995-09-01), Schultz et al.
patent: 5586248 (1996-12-01), Alexander et al.
patent: 6694479 (2004-02-01), Murthy et al.
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