Dual bus computer network using dual busses with dual spy module

Details Dual bus computer network using dual busses with dual spy module Dual bus computer network using dual busses with dual spy module

1996-08-21

1998-04-07

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

364DIG1, 3642318, 3642434, 364964342, 711118, 711141, 711145, 711146, 711154, G06F 1208, G06F 1300

Patent

active

057377561

ABSTRACT:
A system and method for enhancing the rapidity of invalidation cycles in a processor having store-through cache holding 4-word data packets whereby an invalidation queue holds addresses of data to be invalidated in cache and the addresses are supplied by a system bus spy module which monitors the addresses of new data words selected for a write operation.

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