Dual bus memory transactions using address bus for data transfer

Details Dual bus memory transactions using address bus for data transfer Dual bus memory transactions using address bus for data transfer

1996-07-01

1998-03-31

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395281, 395304, 711154, 711167, G06F 1300

Patent

active

057348499

ABSTRACT:
During burst write transactions, a memory accepts data over an address bus after an address has been received. In order to accept data over the address bus, the memory temporarily stores the data received over the address bus in an internal data buffer. The internal data buffer then transfers the data to an array upon completion of the write transaction. During burst read transactions, the memory transmits data over the address bus during one of the four clock cycles after the address is received. In this way a burst write transaction is completed in three clock cycles instead of four. Burst read transactions are completed in four clock cycles instead of five.

REFERENCES:
patent: 4144562 (1979-03-01), Cooper
patent: 4404554 (1983-09-01), Tweedy, Jr. et al.
patent: 4443864 (1984-04-01), McElroy
patent: 4991170 (1991-02-01), Kem
patent: 5249160 (1993-09-01), Wu et al.

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