Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-02-11
1998-09-15
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711142, 711143, 711144, 711145, 711146, 711119, 711120, 711129, 711173, 395308, 39580013, G06F 1316
Patent
active
058095330
ABSTRACT:
A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy unit for maintaining cache coherency and arbiter modules so that any particular module is not starved out. A maintenance processor organizes the network as a joined system where both the store-through and non-store through processor units can utilize either one of the dual system busses or a split system where one bus is dedicated to the store-through processor units and one bus is dedicated to the non-store through processor units.
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Cowgill Richard Allen
Ricci Paul Bernard
Sheth Jayesh Vrajlal
Tran Dan Trong
White Theodore Curt
Kozak Alfred W.
Petersen Steven R.
Starr Mark T.
Swann Tod R.
Tran Denise
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