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Load/store instruction control circuit of microprocessor and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Load/store unit having pre-cache and post-cache queues for...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Load/store unit with multiple oldest outstanding instruction poi

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Loading accessed data from a prefetch buffer to a least...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Loading data to vector renamed register from across multiple...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Local cache-to-cache transfers in a multiprocessor system

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Local emulation of data RAM utilizing write-through cache...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Local invalidation buses for a highly scalable shared cache...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Local region table for storage of information regarding...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Localized cache block flush instruction

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Location-based placement algorithms for set associative...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Lock control apparatus and method including controlling means fo

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Logging of level-two cache transactions into banks of the...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Logic for implementing a dual clock domain read access with...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Look ahead LRU array update scheme to minimize clobber in...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Look-up filter structures, systems and methods for filtering...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Loop cache memory and cache controller for pipelined...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Loosely coupled mass storage computer cluster

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Low complexity speculative multithreading system based on...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Low complexity speculative multithreading system based on...

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