Load/store instruction control circuit of microprocessor and...
Load/store unit having pre-cache and post-cache queues for...
Load/store unit with multiple oldest outstanding instruction poi
Loading accessed data from a prefetch buffer to a least...
Loading data to vector renamed register from across multiple...
Local cache-to-cache transfers in a multiprocessor system
Local emulation of data RAM utilizing write-through cache...
Local invalidation buses for a highly scalable shared cache...
Local region table for storage of information regarding...
Localized cache block flush instruction
Location-based placement algorithms for set associative...
Lock control apparatus and method including controlling means fo
Logging of level-two cache transactions into banks of the...
Logic for implementing a dual clock domain read access with...
Look ahead LRU array update scheme to minimize clobber in...
Look-up filter structures, systems and methods for filtering...
Loop cache memory and cache controller for pipelined...
Loosely coupled mass storage computer cluster
Low complexity speculative multithreading system based on...
Low complexity speculative multithreading system based on...