Loading data to vector renamed register from across multiple...

Details Loading data to vector renamed register from across multiple... Loading data to vector renamed register from across multiple...

2009-04-08

2011-12-27

Phan, Trong (Department: 2827)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S123000, C711S124000, C711S125000, C711S135000, C711S140000, C711S141000

Reexamination Certificate

active

08086801

ABSTRACT:
A load instruction that accesses data cache may be off natural alignment, which causes a cache line crossing to complete the access. The illustrative embodiments provide a mechanism for loading data across multiple cache lines without the need for an accumulation register or collection point for partial data access from a first cache line while waiting for a second cache line to be accessed. Because the accesses to separate cache lines are concatenated within the vector rename register without the need for an accumulator, an off-alignment load instruction is completely pipeline-able and flushable with no cleanup consequences.

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