Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-03-13
2007-03-13
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S005000
Reexamination Certificate
active
11144097
ABSTRACT:
A plurality of processors on a chip is operated in lockstep. A crossbar switch on the chip couples and decouples the plurality of processors to a plurality of banks in a level-two (L2) cache. As data is stored in a first bank of the L2cache, the old data at that location is passed through the crossbar switch to a second bank of the L2cache that is functioning as a first-in-first-out memory (FIFO). Thus, new data is cached at a location in the first bank of the level-two cache, i.e., stored, and old data, from that location, is logged in the second bank of the level-two cache. The logged data in the second bank is used to restore the first bank to a known prior state when necessary.
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Chaudhry Shailender
Jacobson Quinn A.
Saulsbury Ashley
Gunnison Forrest
Gunnison McKay & Hodgson, L.L.P.
Peugh Brian R.
Sun Microsystems Inc.
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