Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-04-26
2011-04-26
Thai, Tuan V (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S167000, C711S168000, C711S149000
Reexamination Certificate
active
07934057
ABSTRACT:
Embodiments of the invention are directed to systems and method for providing predictable timing for read operations in a multiport memory device. Accordingly, an embodiment is directed to a multiport memory system, comprising a single port memory core synchronized to a first clock, multiple access ports synchronized to at least a second clock, and a multiplexer logic coupled to the core memory and the plurality of access ports. The multiplexer logic arbitrates access to the memory core between multiple access ports. Each access ports includes an uncertainty detect logic that measures data path latency, and an uncertainty adjust logic that operates to selectively add data path delay to increase the measured path latency to a predictable value.
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Cypress Semiconductor Corporation
Thai Tuan V
Yu Jae U
LandOfFree
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