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Dual cache directories with respective queue independently execu

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual cache module support for array controller

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual cache with multiple interconnection operation modes

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual comparator scheme for detecting a wrap-around condition and

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual line size cache directory

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual storage apparatus and control method for the dual...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual usage memory selectively behaving as a victim cache for L1

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual XPCS for disaster recovery

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual-L2 processor subsystem architecture for networking system

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual-ported, pipelined, two level cache system

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dual-stack memory architecture and compiling method

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Duplicate snoop tags partitioned across multiple...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Duty cycle controller for clock signal to synchronous SRAM on FP

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dynamic adjustment of prefetch stream priority

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dynamic allocation of home coherency engine tracker...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dynamic allocation of shared cache directory for optimizing...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dynamic arbitration priority

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dynamic cache management in a symmetric multiprocessor...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dynamic cache partitioning

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Dynamic cache partitioning

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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