Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-12-22
1998-04-14
Auve, Glenn A.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711151, G06F 1300
Patent
active
057403830
ABSTRACT:
An arbitration controller that temporarily raises the priority of a graphic device's HWM request above that of the BitBLT engine while that device's LWM request is being served. In this manner, the BitBLT engine cannot interrupt the transfer of data to the graphics device. Each device capable of issuing memory access requests is categorized into one of four classes. The LWM requests are the highest priority requests, followed by CPU memory access requests, then BitBLT engine requests, and finally by HWM requests. When a LWM request is granted, the requesting device's HWM request is elevated to a priority between the CPU and the BitBLT engine. Once the LWM request is complete, the HWM request is served until either it completes, the CPU issues a memory access request, or another LWM request occurs.
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Berk Douglas Michael
Hamilton Douglas
Nally Robert Marshall
Nelsen Pete Edward
Auve Glenn A.
Cirrus Logic Inc.
Ford Stuart J.
Shaw Steven A.
Tannenbaum David H.
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