Duty cycle controller for clock signal to synchronous SRAM on FP

Details Duty cycle controller for clock signal to synchronous SRAM on FP Duty cycle controller for clock signal to synchronous SRAM on FP

1998-02-09

1999-08-17

Butler, Dennis M.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395559, 711100, G06F 104

Patent

active

059406062

ABSTRACT:
A duty cycle controller for generating proper control signals for an SRAM in an FPGA in the proper sequence and spaced at the proper times to guarantee proper operation of the SRAM regardless of the frequency of duty cycle of the clock selected by the user to synchronize and drive operations of the SRAM.

REFERENCES:
patent: 5416744 (1995-05-01), Flannagan et al.
patent: 5650971 (1997-07-01), Longway et al.
patent: 5754838 (1998-05-01), Shibata et al.

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