Dual usage memory selectively behaving as a victim cache for L1

Details Dual usage memory selectively behaving as a victim cache for L1 Dual usage memory selectively behaving as a victim cache for L1

1996-01-25

1998-10-13

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711138, G06F 1208

Patent

active

058227555

ABSTRACT:
A microprocessor architecture including a first cache memory disposed on-chip for storing data along with an associated on-chip tag memory. A second memory is provided on-chip for storing data in a first mode of operation and for storing tags relating to the contents of a second cache memory in a second mode of operation. The mode of operation is set by control logic. The mode is selected by setting a bit in a mode control register. When the bit is set, the control logic changes the system from a first mode in which the second memory serves as additional on-chip cache memory to a second mode in which the second memory stores tags for an external level 2 cache memory. The invention provides a flexible cache structure in which increased on-chip cache is provided or tag memory area is provided for an off-chip level 2 cache.

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