Dual-stack memory architecture and compiling method

Details Dual-stack memory architecture and compiling method Dual-stack memory architecture and compiling method

2006-03-28

2006-03-28

Nguyen, T (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S217000, C711S170000

Reexamination Certificate

active

07020747

ABSTRACT:
Briefly, embodiments of the invention provide an architecture including two or more stack memories defined on separate memory banks. An apparatus in accordance with embodiments of the invention may include, for example, a processor associated with two stack memories defined on separate single-access memory banks. Embodiments of the invention further provide a method of compilation including, for example, allocating a first variable to a first memory bank and allocating a second variable to a stack memory defined on a second memory bank.

REFERENCES:
patent: 5214786 (1993-05-01), Watanabe et al.
patent: 5287309 (1994-02-01), Kai
patent: 6167488 (2000-12-01), Koppala

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