Input/Output completion system for a data processing platform
Input/output decoupling system method having a cache for...
Instruction set for programmable queuing
Integrated circuit design structure for an asychronous data...
Integrated circuit device having two or more input ports and...
Integrated circuit FIFO memory devices that are divisible...
Integrated FIFO memory management control system using a...
Intelligent scaleable FIFO buffer circuit for interfacing betwee
Interface apparatus for connecting devices operating at...
Interface circuit for card-type memory, ASIC including...
Interface for industrial controller network card
Interrupt driven interface coupling a programmable media...
Lane to lane deskewing via non-data symbol processing for a...
Lane to lane deskewing via non-data symbol processing for a...
Lane to lane deskewing via non-data symbol processing for a...
Latency control circuit and method using queuing design method
Latency insensitive FIFO signaling protocol
Link layer controller that provides a memory status signal...
Lockless access to a ring buffer
Logical output queues linking buffers allocated using free lists