Latency insensitive FIFO signaling protocol

Details Latency insensitive FIFO signaling protocol Latency insensitive FIFO signaling protocol

2005-05-11

2008-11-18

Sorrell, Eron J (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S053000, C710S058000, C710S060000

Reexamination Certificate

active

07454538

ABSTRACT:
Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.

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Newton, Harry, Newton's Telecom Dictionary, Feb. 2002, CMP books, 18th Edition, p. 682.

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