Lane to lane deskewing via non-data symbol processing for a...
Lane to lane deskewing via non-data symbol processing for a...
Lane to lane deskewing via non-data symbol processing for a...
Latency control circuit and method using queuing design method
Latency insensitive FIFO signaling protocol
Link layer controller that provides a memory status signal...
Lockless access to a ring buffer
Logical output queues linking buffers allocated using free lists
Low latency FIFO circuit for mixed clock systems
Low latency queue pairs for I/O adapters
Low latency send queues in I/O adapter hardware