Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2000-12-11
2004-06-22
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S033000, C710S053000, C710S060000
Reexamination Certificate
active
06754740
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an interface apparatus for connecting devices operating at different clock rates, and in particular to an interface apparatus for connecting a clocked device provided with an asynchronous bus to a clocked peripheral device provided with a synchronous bus. In addition, the present invention also relates to a method for operating such an interface apparatus.
BACKGROUND OF THE INVENTION
Many digital processor devices like for example digital signal processors (hereinafter referred to as DSP) are provided with an asynchronous data bus which is controlled by timing control signals. In connection with such an asynchronous bus certain difficulties may arise in application situations which have strict timing requirements. For example, when a data bus of a DSP device has to be connected to an Application Specific Integrated Circuit device (hereinafter referred to as ASIC device), which uses only synchronous memory means controlled by a clock signal, timing and/or connection problems may arise.
According to a principle interface that is common to DSP processors of various manufacturers (like, e.g. processors of the DSP
—
16XX family manufactured by AT&T® or, as a further example, DSP processors provided by Texas Instruments®), an asynchronous data bus of a DSP is controlled by the following signals: signal ADDRESS: specifying the address of memory means (a memory or register) to which data signals DATA are to be written and/or read from; signal RWN (read/write): specifying that dependent on its currently set value (“0” or “1”) the DSP processor performs a data transfer operation, i.e. either a write operation or a read operation to or from a peripheral circuit device like an ASIC device and the memory means provided therein; and signal ENA: specifying, dependent on its binary value, whether the DSP device carries out a read/write operation at all, i.e. indicating whether the DSP device is active (ENA=0) or inactive (ENA=1).
The DSP processor also provides a clock signal CKO which may be used for clocking the ASIC operation and also to control the interface. Nevertheless, a clock signal CLK for clocking the ASIC device could be generated elsewhere, such that clock signals supplied to the ASIC device (CLK) and the DSP device (CKO) originate from different sources, respectively. Then, the DSP device and the ASIC device can be independently clocked, and even clocked at different clock rates. Nevertheless, in such a case both devices (DSP and ASIC) could operate with the same clocks and could even be synchronous to each other. In this connection, it has to be noted that for simplified description, the signal CLK for clocking the ASIC device is described hereinafter as if being provided by the DSP device, while this does not limit the invention to such an arrangement.
A schematic block diagram of an ASIC device
3
as a device provided with synchronous memory means
3
a
being connected via an interface apparatus (I/F)
2
to a DSP device
1
provided with an asynchronous data bus (not shown) is depicted in FIG.
1
.
Previously, several interface apparatuses have been proposed for the purpose of interconnecting a DSP device to an ASIC device.
For example, EP-A1-0 649 097 relates to a synchronous approach and discloses an interface between unsynchronized devices, which interface comprises a delay means for synchronizing the write strobe of the first device with the system clock of the second device.
Furthermore, another synchronous approach is proposed in WO-A-96/38793 of the present applicant. According to the method and apparatus for adapting an asynchronous bus to a synchronous circuit as disclosed therein, the timing control signals of the DSP data bus are synchronized to the system clock signal CLK using a flip-flop arrangement.
Moreover, apart from synchronous interfaces, a type of interfaces based on an asynchronous approach has been proposed by the present applicant. In particular, such an asynchronous interface is described in a recent Finnish patent application (FI 972091 filed May 15, 1997) of the same applicant, the present inventor being a co-inventor thereof. As disclosed therein, an asynchronous state machine creates additional signals for internal use in the interface apparatus and/or ASIC device, based on the supplied signals ENA and RWN. In particular, a signal that may be used for burst type read operations from a memory as a clock signal of, for example, an autoincrement counter is generated.
The above mentioned previous solutions, however, merely solved the problem of providing an asynchronous interface, while these solutions will no longer work reliably if the clock rate of the DSP device is much faster than the clock rate of the ASIC device. That is, problems caused due to different clock speeds between the DSP device and the ASIC device can not be prevented by these interface apparatuses.
For example, the DSP device clock frequency is suggested to be 90 MHz, while the ASIC device clock frequency is suggested to be 50 MHz. Since the DSP device may write data with nearly double speed as compared to the ASIC device reading speed, this means that for every writing operation period an extra period of no operation or a “no operation” instruction (hereinafter NOP period/instruction) is required.
This problem will become more and more severe in future when the processing capacity of the used DSP devices is overloaded and it is required to increase the clock frequency of the DSP devices without a possibility to increase the clock frequencies of ASIC devices used.
Stated in other words, timing problems become the more severe the greater the difference in clock frequencies between DSP device and the ASIC device to be connected thereto is.
FIG. 2
of the accompanying drawings represents a timing diagram of above mentioned signals according to the method previously proposed and as disclosed in WO-A-96/38793. In particular,
FIG. 2
illustrates a situation, in which there occurs a problem upon connection of a digital ASIC device to a data bus of a DSP device, if the clock frequency of the ASIC device is significantly lower than the clock frequency of the DSP device. As already briefly explained further above, the signal ENA is the DSP device enable signal, indicative of whether the DSP device is active or not with regard to a data transfer operation, i.e. a writing/reading operation to/from the ASIC device; the signal RWN is the signal specifying the writing/reading operation when the DSP device is enabled; ADDRESS indicates the signal transmitted on the address bus of the DSP device; DATA represents the signal transmitted on the data bus of the DSP device; CLK is the system clock of the ASIC device (provided by the DSP device or from an independent external clock signal generating means, as mentioned above). These signals are provided and/or transmitted by the DSP device. Signals ADDRESS
1
, ADDRESS
2
, and DATA
1
, DATA
2
, indicate address and data values, respectively, applied to the ADDRESS and DATA signal lines, respectively, during periods, during which a specific data is to be written to and/or read from a corresponding specific address in a memory means.
The additionally depicted signal WR_ENABLE is an internal signal generated by the interface apparatus and used only internally within the ASIC device and the interface device. The signal WR_ENABLE actually enables the writing of transmitted data to a memory means of the ASIC device after synchronization.
As shown in the timing diagram, two subsequent writing operations are to be performed: writing DATA
1
to ADDRESS
1
, followed by writing DATA
2
to ADDRESS
2
. Writing is instructed when the signal ENA assumes a low value (“0”), thereby enabling the DSP device and when simultaneously the signal RWN assumes a low value (“0”), thereby instructing writing of data to a memory means. On the other hand, a pair of signal values (ENA, RWN)=(
0
,
1
) represents a reading operation from a memory means, while signal values (ENA, RWN)=(
1
,X) represen
Gaffin Jeffrey
Patel Niketa I.
Squire Sanders & Dempsey L.L.P.
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