Integrated FIFO memory management control system using a...

Details Integrated FIFO memory management control system using a... Integrated FIFO memory management control system using a...

2005-04-05

2005-04-05

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S052000, C710S053000, C710S054000, C710S055000, C710S057000

Reexamination Certificate

active

06877049

ABSTRACT:
An integrated data controller that utilizes a first-in first-out (FIFO) management system that compensates for the unpredictable nature of latency associated with requesting data from memory and enables the timing of data requests to be determined based on the number of pending requests and the amount of data currently residing in the buffer. The FIFO management system includes a FIFO controller and a FIFO buffer that monitor a credit value and a trigger value to determine when to make data request bursts upon a memory unit. The trigger value is an indication of whether there is a sufficient amount of free space for it to be beneficial to make a data request burst and the credit value is a number that indicates the number of a data blocks that should be requested in the data request burst.

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