Latency control circuit and method using queuing design method

Details Latency control circuit and method using queuing design method Latency control circuit and method using queuing design method

2011-07-12

2011-07-12

Sorrell, Eron J (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C365S194000

Reexamination Certificate

active

07979605

ABSTRACT:
A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

REFERENCES:
patent: 6262938 (2001-07-01), Lee et al.
patent: 2005/0138255 (2005-06-01), Moyer et al.
patent: 2005/0160245 (2005-07-01), Artieri
patent: 2007/0085587 (2007-04-01), Lee
patent: 03-091188 (1991-06-01), None
patent: 2002-150763 (2002-05-01), None
IBM, Speculative Latency Measurement Method and Apparatus, Oct. 10, 2002, IBM, pp. 1-4.
English language abstract of Japanese Publication No. 03-091188.
English language abstract of Japanese Publication No. 2002-150763.

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