Intelligent scaleable FIFO buffer circuit for interfacing betwee

Details Intelligent scaleable FIFO buffer circuit for interfacing betwee Intelligent scaleable FIFO buffer circuit for interfacing betwee

1998-08-24

2000-09-05

Etienne, Ario

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

710 52, 710 55, 710 56, 710 57, 3642386, 3642387, 3642388, 3642397, G06F 506, G06F 501, G06F 1200

Patent

active

061157600

ABSTRACT:
The circuit provides a scaleable buffer coupled between digital domains that require data buffering because they operate at different data transfer rates and/or because one or more of the digital domains uses data bursting. The scaleable buffer circuit does not have a large fixed throughput latency as is characteristic of a first-in-first-out buffer. The buffer includes serially coupled burst cells each having a sequential element, a controlled multiplexer and control logic for controlling the multiplexer and for generating output control signals. In one embodiment, the control circuit is a finite state machine. Each burst cell is capable of receiving data from an upstream burst cell or from the input data bus. Therefore, the buffer can be filled starting from its most downstream and vacant burst cell rather than always starting from the most upstream cell (as in a typical FIFO). This reduces the throughput latency of the buffer in cases when it is not always full. By using burst cells, rather than a dual ported RAM, the interface circuitry is significantly reduced in complexity. Each burst cell is uniform in construction and contains distributed interface circuitry making the circuit readily scaleable in size without redesigning the interface circuitry.

REFERENCES:
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patent: 5021684 (1991-06-01), Ahuja et al.
patent: 5144525 (1992-09-01), Saxe et al.
patent: 5256916 (1993-10-01), Thurston
patent: 5345554 (1994-09-01), Lippincott et al.
patent: 5835498 (1998-11-01), Kim et al.

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