Integrated circuit design structure for an asychronous data...

Details Integrated circuit design structure for an asychronous data... Integrated circuit design structure for an asychronous data...

2011-06-21

2011-06-21

Kindred, Alford W (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C703S001000, C703S014000, C710S055000

Reexamination Certificate

active

07966435

ABSTRACT:
A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, the design structure comprising for an interface system is disclosed. The system includes a buffer that receives data from a source in a first clock domain and stores the data to be read by a destination in a second clock domain, wherein the buffer functions in both the first clock domain and the second clock domain; a write pointer that points to data written by the source; and a read pointer that points to data read by the destination. According to the design structure, the write pointer and the read pointer are utilized to enable the data to be transmitted from the first clock domain to the second clock domain asynchronously.

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