Structure for a stacked power clamp having a BigFET gate...
Structure for a system for controlling access to addressable...
Structure for a voltage detection circuit in an integrated...
Structure for an absolute duty cycle measurement circuit
Structure for an integrated circuit design for reducing...
Structure for automated transistor tuning in an integrated...
Structure for couple noise characterization using a single...
Structure for dynamic latch state saving device and protocol
Structure for estimating power consumption of integrated...
Structure for fractional-N phased-lock-loop (PLL) system
Structure for glitchless clock multiplexer optimized for...
Structure for imagers having electrically active optical...
Structure for implementing speculative clock gating of...
Structure for improved capacitance and inductance calculation
Structure for initializing expansion adapters installed in a...
Structure for integrated circuit for measuring set-up and...
Structure for interleaved voltage controlled oscillator
Structure for on-chip electromigration monitoring system
Structure for optimizing the signal time behavior of an...
Structure for partitioned dummy fill shapes for reduced mask...