Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-18
2011-01-18
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C327S143000
Reexamination Certificate
active
07873921
ABSTRACT:
A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
REFERENCES:
patent: 3571626 (1971-03-01), Reif
patent: 3622805 (1971-11-01), McMorrow, Jr.
patent: 3828204 (1974-08-01), Farnsworth
patent: 3879669 (1975-04-01), Moriyasu
patent: 4063119 (1977-12-01), Odell et al.
patent: 4142118 (1979-02-01), Guritz
patent: 4694198 (1987-09-01), Umeki
patent: 5116342 (1992-05-01), Schmidt et al.
patent: 5144159 (1992-09-01), Frisch et al.
patent: 5214316 (1993-05-01), Nagai
patent: 5336942 (1994-08-01), Khayat
patent: 5365121 (1994-11-01), Morton et al.
patent: 5703807 (1997-12-01), Smayling et al.
patent: 6002292 (1999-12-01), Allen et al.
patent: 6172555 (2001-01-01), Gusinov
patent: 6285222 (2001-09-01), Kitade
patent: 6335649 (2002-01-01), Maeda
patent: 6472912 (2002-10-01), Chiu et al.
patent: 6549040 (2003-04-01), Alvandpour et al.
patent: 6577480 (2003-06-01), Avery et al.
patent: 6650155 (2003-11-01), Nguyen et al.
patent: 6756839 (2004-06-01), Hall et al.
patent: 6801060 (2004-10-01), Ikehashi et al.
patent: 7030668 (2006-04-01), Edwards
patent: 7049865 (2006-05-01), Parker et al.
patent: 7061308 (2006-06-01), Abadeer et al.
patent: 7187219 (2007-03-01), Olsen
patent: 7207017 (2007-04-01), Tabery et al.
patent: 7466171 (2008-12-01), Abadeer
patent: 7498869 (2009-03-01), Abadeer et al.
patent: 2003/0030474 (2003-02-01), McGowan
patent: 2003/0122595 (2003-07-01), Hall et al
patent: 2004/0041590 (2004-03-01), Bernstein et al.
patent: 2004/0104744 (2004-06-01), Bosshart
patent: 2004/0222827 (2004-11-01), Degoirat et al.
patent: 2004/0263208 (2004-12-01), Levy et al.
patent: 2004/0263209 (2004-12-01), Choe
patent: 2005/0073354 (2005-04-01), Abadeer et al.
patent: 2006/0170487 (2006-08-01), Abadeer
patent: 2006/0214695 (2006-09-01), Lih et al.
patent: 2006/0290385 (2006-12-01), Belluomini et al.
patent: 2008/0169837 (2008-07-01), Abadeer
patent: 2008/0169839 (2008-07-01), Abadeer
patent: 2008/0169844 (2008-07-01), Abadeer et al.
patent: 2008/0169869 (2008-07-01), Abadeer
patent: 2008/0229269 (2008-09-01), Lamorey
patent: 2009/0021289 (2009-01-01), Abadeer et al.
First Office Action dated Jan. 7, 2010, with regard to related U.S. Appl. No. 12/242,114, filed Sep. 30, 2008, entitled Voltage Detection Circuit in an Integrated Circuit; Wagdi Abadeer et al.
Response to Office Action and Terminal Disclaimer dated Apr. 5, 2010, with regard to related U.S. Appl. No. 12/242,114, filed Sep. 30, 2008, entitled Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal; Abadeer.
Notice of Allowance dated Apr. 3, 2009, in connection with related U.S. Appl. No. 11/623,112.
U.S. Appl. No. 11/623,119, filed Jan. 15, 2007 entitled “Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal,” Wagdi W. Abadeer, Jeffrey S. Brown, Albert M. Chu, John A. Fifield.
Final Office Action dated Jun. 2, 2010, with regard to related U.S. Appl. No. 12/242,114, filed Sep. 30, 2008, entitled Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal; Abadeer.
First Office Action dated Apr. 21, 2008 in connection with related U.S. Appl. No. 11/623,119.
Response to First Office Action dated May 30, 2008 in connection with related U.S. Appl. No. 11/623,119.
Notice of Allowance dated Jul. 31, 2008 in connection with related U.S. Appl. No. 11/623,119.
Related U.S. Appl. No. 12/242,114, filed Sep. 30, 2008 entitled Voltage Detection Circuit in an Integrated Circuit; Wagdi Abadeer et al.
K.E. Kuijk, “A Precision Reference Voltage Source,” IEEE Journal of Solid-State Circuits, vol. SC-8, pp. 222-226, Jun. 1973.
H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, K. Sakui, “A CMOS Bandgap Reference Circuit with Sub-1-V Operation,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999, pp. 670-674.
First Office Action dated Apr. 30, 2008 in connection with related U.S. Appl. No. 11/623,114.
Response to First Office Action dated Jun. 12, 2008 in connection with related U.S. Appl. No. 11/623,114.
Notice of Allowance dated Oct. 16, 2008 in connection with related U.S. Appl. No. 11/623,114.
C.H. Kim, K. Roy, S. Hsu, A. Alvandpour, R.K. Krishnamurthy, S. Borkar, “A Process Variation Compensating Technique for Sub-90 nm Dynamic Circuits,” VLSI Circuits, 2003. Digest of Technical Papers, 2003 Symposium on Jun. 12-14, 2003, pp. 205-206.
V. Kursun, E.G. Friedman, “Domino Logic With Dynamic Body Biased Keeper,” Solid-State Circuits Conference 2002, ESSCIRC 2002. Proceedings of the 28th European, Sep. 24-26, 2002, pp. 675-678.
Office Action dated May 16, 2008 with regard to related U.S. Appl. No. 11/851,133.
Amendment under 37 C.F.R. 1.111 with regard to related U.S. Appl. No. 11/851,133, Jun. 13, 2008.
Notice of Allowance dated Jul. 31, 2008 with regard to related U.S. Appl. No. 11/851,133.
First Office Action dated Jan. 23, 2008 with regard to related U.S. Appl. No. 11/623,112.
Response to First Office Action dated Apr. 14, 2008 with regard to related U.S. Appl. No. 11/623,112.
Second Office Action dated Jul. 31, 2008 with regard to related U.S. Appl. No. 11/623,112.
Response to Final Office Action dated Jul. 19, 2010, with regard to related U.S. Appl. No. 12/242,114, filed Sep. 30, 2008, entitled “Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal”; Abadeer.
Notice of Allowance dated Aug. 2, 2010, in connection with related U.S. Appl. No. 12/242,114, filed Sep. 30, 2008, entitled “Voltage Detection Circuit in an Integrated Circuit and Method of Generating a Trigger Flag Signal,” Abadeer.
Abadeer Wagdi W.
Brown Jeffrey S.
Chu Albert M.
Fifield John A.
Downs Rachlin & Martin PLLC
International Business Machines - Corporation
Whitmore Stacy A
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