Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-12-03
2001-08-28
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06282692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the electrical/electronic device packaging arts in general, including manufacture of printed circuit cards and boards, and more particularly, to an improved structure for calculating the capacitance and inductance of a wide variety of structures found in computers, microwave and other electronic devices.
2. Discussion of the Prior Art
The computation of electrical properties, e.g., capacitance and inductance, is a central part of modeling behavior of electrical circuits and structures found in VLSI chip and package interconnects as well as microwave circuits, PC cards, boards, ceramic and other chip carriers. These structures typically include: conductors, arranged as signal lines that are predominantly rectangular in nature and can be subdivided into rectangular subsections for the purposes of electrical analysis; ground (power) planes, and vias for interconnecting the signal lines or ground planes which also may be approximated as rectangular, and an insulating dielectric. Depending on the application, the signal line structures lie in planes parallel to the ground planes and may run at arbitrary angles, e.g., 45°, relative to the ground plane. In addition, the ground plane may be solid or have cutouts (apertures).
Present inductance calculation techniques for 3-dimensional structures typically involve calculating a return current distribution using a numerical simulation of the structure and a given numerical grid which subdivides the structure into cells, with each cell supporting a constant current. Assuming a highly accurate numerical technique, e.g., the method-of-moments technique, the calculated results when utilizing an ultra-fine grid should be the same as the true current distribution, which may be obtained, e.g., by direct measurement. As known, the method-of-moments technique involves the generation and subsequent solution of a matrix equation with the currents on each cell as the unknowns. Thus, for a 3D example structure including an x-y finite ground plane apportioned as rectangular grid having 20×20 current elements, with each current element having a unit current and an associated coefficient in both x and y directions, a current distribution calculation in the ground plane would involve the solution of a matrix of equations with about 800 unknowns. Generating more accurate results for the current distribution generally requires the implementation of a ground plane portion having a finer current element grid, e.g., 40×40. In the case of a 40×40 current element grid, for example, the current distribution calculation would require the solution of a matrix equation having about 3200 unknowns. As can be surmised, a grid sufficiently fine for accurate results increases computation run time and storage requirements, e.g., when implementing standard techniques, doubling the number of unknowns yields a factor of eight increase in run time and a factor of four increase in storage requirements. Oftentimes, the problem to be solved becomes too large to run.
When the modeled structure consists of diagonal lines run over a finite ground plane, further problems are introduced because the rectangles into which the ground plane and signal line are subdivided do not overlap in a projection sense. Because of this, the return current that must exist in the ground plane cannot closely enough match the true current. That is, the return current is more stair-case in nature as opposed to smoothly diagonal, and this in general leads to higher values of self inductance and substantial errors in the coupling inductance calculations. The problem becomes more severe as the signal lines get closer to the ground planes or other signal lines. Simulations demonstrate that the problem occurs when the height of the signal line above the ground plane is less than the grid size associated with the rectangles in the ground plane. Under these circumstances, accurate solutions can only be obtained using very fine grids which leads to excessive computer run times and storage requirements.
The accuracy of the method of moments solution for structures involving diagonal lines has heretofore not been sufficiently addressed by those in this art. Alternative solutions to the problem exist, and include the use a finer ground plane grid, the use of a more general set of basis functions in the moment-method analysis, and the use of other analysis techniques, such as finite element. The last two alternatives make use of non-rectangular basis functions, such as triangles or tetrahedrals. The use of such basis functions allows both the diagonal line and ground plane to be sectioned in such a way that the return current can be accurately modeled, however, problems exist with all of these alternatives. For example, codes that employ triangular or other basis functions are generally inferior to those based on rectangular basis functions when applied to structures that are predominantly rectangular in nature; they are not as accurate, may introduce false asymmetries, and require more unknowns to model rectangular regions. The finite element technique is not appropriate for all problems, especially those that involve high aspect ratios, and this occurs when long and narrow signal lines are present. Further, the use of such techniques, even when appropriate, means that additional codes must be purchased or developed by the entity performing the modeling. Once employed, these results must be reconciled against those of rectangular structures where the rectangle-based tools were used.
For capacitance calculations, a similar set of arguments apply, except a charge distribution is considered rather than current distribution.
It would be desirable to provide a highly accurate technique for analyzing electrical circuit properties, e.g., inductance and capacitance, of circuits and device structures that is computationally efficient and readily implementable in conventional 3D package analysis programs.
It would be desirable to provide a highly accurate technique for analyzing electrical circuits and structures that lie diagonal with respect to a finite ground plane.
SUMMARY OF THE INVENTION
The present invention is directed to a methodology and circuit modeling structure for analyzing the packaging of electrical circuits and determining electrical circuit properties, e.g., inductance and capacitance, of circuits and circuit structures found in VLSI chips, PC cards, boards, microwave circuits, etc. The methodology and circuit modeling structure is readily implemented in 3D circuit package analysis programs and provides a computationally efficient way to analyze complex types electrical/electronic/packaging circuits and structures. Such circuits and structures include those electrical structures that lie diagonally with respect to a finite ground plane. Such a circuit modeling structure is readily implementable in analysis techniques, including method-of-moments, and finite element analysis.
According to the principles of the invention there is provided a system and method for automatically improving the computational accuracy of electrical properties associated with an electrical circuit including a signal line structure capable of carrying current and a ground plane for having a return current distribution, including: locating one or more signal line structures each for carrying current near a ground plane structure and located a distance h relative thereto; associating one or more shadow line structures with each signal line structure and locating the one or more shadow line structures an infinitesimal distance above or below said ground plane running in parallel with its associated signal line structure, the ground plane and associated shadow line structures defined as carrying return current; each shadow line structure having a first via structure for connecting a first end of the shadow line to the ground plane, and a second via structure connecting a second end of the shadow line to the ground plane; and, inputt
International Business Machines - Corporation
Kik Phallaka
Morris, Esq. Daniel P.
Scully Scott Murphy & Presser
Smith Matthew
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