Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-16
2010-12-28
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07861208
ABSTRACT:
A design structure, method, and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. A design structure is embodied in a machine readable medium used in a design process, the design structure comprising regions in a finished semiconductor design that do not contain as-designed shapes. The design structure additionally includes dummy fill shapes in the regions at a predetermined final density, wherein the generated dummy shapes are sized so that their local density is increased to a predetermined value. Moreover, corresponding trim shapes act to expose an oversized portion of the dummy shape, effectively trimming each dummy shape back to the predetermined final density.
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Faure Thomas B.
Landis Howard S.
Sucharitaves Jeanne-Tania
International Business Machines - Corporation
Kotulak Richard
Roberts Mlotkowski Safran & Cole, P.C
Sandoval Patrick
Siek Vuthe
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