Measuring integrated circuit layout efficiency
Mechanism for detection and compensation of NBTI induced...
Mechanism for recognizing and abstracting pre-charged...
MEEF reduction by elongation of square shapes
Memory architecture permitting selection of storage density...
Memory characterization system
Memory compiler with ultra low power feature and method of use
Memory controller with variable zone size
Memory debugger for system-on-a-chip designs
Memory efficient array transposition via multi pass tiling
Memory embedded semiconductor integrated circuit and a...
Memory generation and placement
Memory macro with irregular edge cells
Memory re-implementation for field programmable gate arrays
Memory tiling architecture
Memory timing model with back-annotating
Memory-saving method and apparatus for partitioning high fanout
Merging a hardware design language source file with a...
Merging multiplexers to reduce ROM area
Merging multiplexers to reduce ROM area