Memory macro with irregular edge cells

Details Memory macro with irregular edge cells Memory macro with irregular edge cells

2011-03-22

2011-03-22

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S119000

Reexamination Certificate

active

07913215

ABSTRACT:
A memory macro includes a first set of cells disposed in a first area of a memory array, and a second set of cells, which differ from the first set of cells in physical dimensions, disposed at an edge of the first area for improving robustness of the cells at the edge of the memory array.

REFERENCES:
patent: 6411556 (2002-06-01), Amano
patent: 6519746 (2003-02-01), Andreev et al.
patent: 7313769 (2007-12-01), Lukanc et al.
patent: 7404154 (2008-07-01), Venkatraman et al.
patent: 2002/0053691 (2002-05-01), Leung et al.

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