Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-07
2003-03-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06536013
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for designing a memory embedded semiconductor integrated circuit, which clarifies the conditions that ought to be fulfilled by superior designs/fabrication techniques, and enables selection from a number of techniques the ones suitable to the scales of the memory and the logic circuit during the development of a memory embedded logic LSI, as well as a memory embedded semiconductor integrated circuit as an application of the same method.
2. Description of the Related Art
As memory cells able to be integrated (embedded) in one chip together with logic gates, there exist chiefly SRAM cells and DRAM cells. In addition, there also exist other such types of memory cells, such as three transistor type memory cells, and various nonvolatile memory cells.
The type of memory cell is one of the element techniques that ought to be selected, or ought to be developed when a memory embedded LSI is developed.
However, when a memory embedded LSI is designed or developed, clear criteria does not exist concerning the questions of under what conditions a certain technique is superior to others, and what superior techniques are.
Concerning the memory LSI for exclusive use, such as DRAM, etc., all efforts have been devoted to reducing the cell size provided that the fabrication processes are not made too sophisticated.
On the other hand, for the memory embedded LSI, the consistency with logic processes also should be considered in addition to the balance between reducing the cell area and avoiding the sophistication of fabrication processes, just like the memory LSI for exclusive use.
In practice, because there are not definite criteria about which technique should be selected, in many cases, selections have been made solely relying on the experiences of developers. In addition, when a new element technique is developed, the rich experiences and high degree decisions of the developers are required, for example, to decide definitely where to attain the balance between the cell area and process simplification.
Concerning the development of memory embedded LSI, there also are other subjects in addition to attaining a balance between reducing the cell area and securing the consistency of processes.
For example, in a nonvolatile memory, it is still a problem that should be solved that there are not definite guidelines for attaining the balance between the process consistency and the transistor's structure parameters and size, which are concerned with the characteristics of high speed transistors used in logic circuit, and high voltage resistance transistors and low voltage resistance transistors used in memory transistors and memory peripheral circuits.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for designing a memory embedded semiconductor integrated circuit, the same method clarifying the conditions for the element techniques to be technically superior, and making it easy to establish the guideline for selecting the superior techniques, thus enabling easy developments during the development of a memory embedded semiconductor integrated circuit, and to provide a memory embedded semiconductor integrated circuit which fulfills the requirements of technique superiority, as an application of the same method.
According to a first aspect of the present invention, there is provided a method for designing a memory embedded semiconductor integrated circuit having a first region where logic gates are formed, a second region where memory cells are formed, and a third region including all other regions but the first region and the second region, the method comprising the steps of: defining a total resource of a fabrication technique by utilizing various numerical values represented by the process number or mask number required for fabricating the memory embedded semiconductor integrated circuit; deducing a unit resource by dividing the total resource by the effective wafer area; defining a first effective technique resource, a second effective technique resource, and a third effective technique resource by multiplying the unit resource by the area of the first region, the area of the second region, and the area of the third region, respectively; comparing a plurality of techniques concerning fabrication and/or design by using the first to the third effective technique resources obtained as these techniques are employed; and selecting from the plurality of techniques those suitable to the required scales of the memory and the logic circuit.
Preferably, the method comprises the steps of: subtracting the effective technique resources of the technique for comparison from the effective technique resources of the technique under investigation and deducing the differences with respect to each of the first to the third effective technique resources; and adopting the technique under investigation under the condition that the sum of the differences over the first to the third regions is negative.
Specifically, the method comprises the steps of: denoting the following equation (1) by the following procedures;
[
CWU
(
n
)
×
SPLG
(
n
)
-
CWU
(
i
)
×
SPLG
(
i
)
]
×
NLG
+
[
CWU
(
n
)
×
SPB
(
n
)
-
CWU
(
i
)
×
SPB
(
i
)
]
×
NMB
+
[
CWU
(
n
)
×
SP
&
IO
(
n
)
-
CWU
(
i
)
×
SP
&
IO
(
i
)
]
<
0
(
1
)
by CWU(n) the unit resource obtained by dividing the total resource of the fabrication technique by the effective wafer area when the memory embedded semiconductor integrated circuit is fabricated by using technique N that is under investigation, by CWU(i) the unit resource when performing fabrication using the i-th technique I among a number of m (m: a natural number) techniques that are for comparison, by SPLG(n) the area per logic gate in the first region when technique N is employed, by SPLG(i) the area per logic gate in the first region as technique I is employed, by SPB(n) the area per memory bit in the second region as technique N is employed, by SPB(i) the area per memory bit in the second region as technique I is employed, by SP&IO(n) the area of the third region as technique N is employed, by SP&IO(i) the area of the third region as technique I is employed, by NLG the total number of the logic gates in the first region, and by NMB the total number of the memory bits in the second region; and adopting the technique N under the condition of satisfying the equation (1).
The method comprises a step of adopting the technique N under the condition of satisfying the equation (2), replacing equation (1),
[
CWU
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n
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-
CWU
(
i
)
]
×
SPLG
×
NLG
+
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[
CWU
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n
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×
SPB
(
n
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-
CWU
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i
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×
SPB
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i
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×
NMB
+
[
CWU
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n
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×
SP
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IO
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n
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-
CWU
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×
SP
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i
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(
2
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when the areas per logic gate SPLG(n) and SPLG(i) being equal, and denoting this area by SPLG.
Furthermore, the method comprises the steps of: denoting the area of the third region by SP&IO when SP&IO(n) is equal to SP&IO(i); and adopting the technique N under the condition of satisfying the equation (3), replacing equation (1),
[
CWU
(
n
)
×
SPLG
(
n
)
-
CWU
(
i
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×
SPLG
(
i
)
]
×
NLG
+
[
CWU
(
n
)
×
SPB
(
n
)
-
CWU
(
i
)
×
SPB
(
i
)
]
×
NMB
+
[
CWU
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n
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-
CWU
(
i
)
]
×
SP
&
IO
(
NLG
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NMB
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<
0
(
3
)
when there are almost not differences in the scales of the logic on board in the first region and in the capacities of the memories on board in the second region, no matter which of technique N and technique I is employed.
On the other hand, the method comprises the steps of: denoting the area of the third region by SP&IO when SP&IO(n) is equal to SP&IO(i); and adopting the technique N under the condition of
Ikeda Naoshi
Kobayashi Toshio
Kananen, Esq. Ronald P.
Rader & Fishman & Grauer, PLLC
Siek Vuthe
Sony Corporation
Tat Binh C.
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