Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-21
2003-07-15
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C365S063000, C365S154000, C365S230010, C365S230080, C365S185080, C365S185110, C365S185280, C365S200000, C365S201000
Reexamination Certificate
active
06594818
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor memories and to the manufacture of semiconductor memories.
DESCRIPTION OF RELATED ART
Manufacturers of integrated circuit (IC) memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory typically provide different products having different sizes (i.e., different storage capacities). Each memory product generally requires separate development, a unique mask set, and a different manufacturing process. Changing a manufacturing facility from manufacturing one size of memory device to another size of memory device can be time consuming because the mask set and process parameters must be changed. The time required for these changes can reduce manufacturing efficiency and increase the cost of the memory devices. Additionally, the manufacturer of IC memory devices often needs to accurately judge the demand for memory devices of the different sizes. Otherwise, the manufacturer has inventory problems when the demand for memory devices shifts and the manufacturer has too many memory devices of one size and too few of another size.
U.S. Pat. No. 5,801,406 describes a programmable gate array (PGA) architecture that permits manufacture of gate arrays of different sizes on a single wafer. The PGA architecture includes arrays that can be used alone for small devices or combined with other gate arrays on the same wafer to create larger devices. This permits simultaneous manufacture of gate arrays of different sizes and avoids the down time associated with changing mask sets for separate manufacture of different sizes of gate array devices. The ability to combine different numbers of underlying arrays in different devices allows flexibility in the product mix resulting from the fabrication process. However, such techniques have not been used for memory because input/output requirements of memory, for example, for address, data, and clock signals differ from the input/output requirements of gate arrays, and efficient methods for combining memory units on a wafer have not been known. Accordingly, achieving similar efficiencies in the production of memory devices requires further advances.
SUMMARY
The present invention provides methods and structures for manufacturing memory chips of different sizes on a single wafer or using the same masks and processing steps to generate a generic wafer that is adaptable to produce memory chips having a size selected in the final stages of wafer processing. When the generic wafers are fabricated, generic layers form a plurality of memory units. The memory units include memory arrays and peripheral circuitry such as input/output (I/O) circuits, control circuits, decoders, address and data buffers, and/or other peripheral circuits needed in an integrated circuit memory device. In one embodiment, each memory unit alone is not complete but is combined with one or more memory unit to form an IC memory chip. Scribe lanes between the memory units can be left free of active circuitry or may include connecting circuitry between the memory units. Generally, the desired storage capacity of each memory chip determines the area of each chip and whether the wafer will be cut along a scribe lane or the scribe lane will contain connecting circuitry.
When demand requires memory devices of a specific storage capacity, specialized layers, which typically implement electrical interconnections, are fabricated over the generic layers to achieve the demanded storage capacity. The specialized layers interconnect the appropriate number of memory units to function as a single IC memory device. The specialized layers can also disable operation of selected circuit blocks that lie within the area of a chip when the circuit blocks are not required to implement the demanded storage capacity.
One embodiment of the invention is a wafer that includes a plurality of memory units that are separated by the scribe lanes. The memory units are such that forming a first conductive structure on a first set of the memory units and cutting the wafer along the scribe lanes surrounding the first set of memory units forms a complete first memory chip having a first storage capacity. Alternatively, forming a second conductive structure on a second set of the memory units and cutting the wafer along the scribe lanes surrounding the second set of memory units forms a complete second memory chip having a second storage capacity that differs the first storage capacity. Generally, the wafer includes all active circuit elements required for the first or second memory chip, and the conductive structures cross at least one of the scribe lanes to connect active circuit elements in one memory unit to active circuit elements in another memory unit.
The first conductive structure can include a conductive pattern formed with a first mask, while the second conductive structure includes a conductive pattern formed with a second mask.
In one specific embodiment, a fuse structure is connected to the memory units. Forming the first conductive structure in this embodiment includes implementing a first fuse option in the fuse structure. Forming the second conductive structure includes implementing a second fuse option in the fuse structure. Generally, the fuse structure extends across one or more of the scribe lanes to thereby interconnect two or more of the memory units.
Each memory units generally includes memory cores and peripheral circuits, but different memory units can include different peripheral circuits so that when the memory units are used in combination there is less redundancy and so that bonding pad patterns for the different size memory chips are similar. When redundant peripheral circuits are present on the same chip, some of the redundant circuits can be disconnected or otherwise disabled.
The wafer is cut according to the desired size or sizes of memory chips, and each memory chip typically includes an intact scribe lane. Additionally, a larger capacity memory chip can have an edge that would have been inside a smaller memory chip. In particular, such relative positioning of boundaries permits different size memory chips that have similar bonding pad configurations.
Another embodiment of the invention is a memory chip. The memory chip includes a semiconductor substrate and a plurality of generic layers disposed on the semiconductor substrate to form first and second memory units. An interconnect structure connects the first memory unit to the second memory unit and crosses a scribe lane that is intact within the memory chip. The scribe lane corresponds to a region of the substrate and the plurality of layers that lacks active circuit elements and has a width sufficient for a wafer cutting process that separated the integrated memory circuit chip from other integrated memory chips formed in a wafer. The memory chip can further include additional memory units and additional scribe lanes between the memory units.
The memory units in the memory chip may be of two different types. Both types including memory storage arrays, but the different types of memory units include different peripheral circuitry. For example, each of X address buffers, Y address buffer, clock buffers, and control signal buffer may only be implemented in one type of memory unit. The interconnect structure can disable redundant peripheral circuitry.
Another embodiment of the invention is an integrated circuit memory chip including a semiconductor substrate and a plurality of generic layers disposed on the semiconductor substrate to form a first memory unit group and a second memory unit group. Each memory unit group can contain one or more memory units. The first memory unit group includes a first structure such as an address buffer, clock buffer, or control signal buffer that is identical to a second structure in the second memory unit. An interconnect structure that connects the first memory unit group to the second memory unit group disables the first structure in the first memory unit group and enables the second structure i
Byun Hyun-Geun
Cho Uk-Rae
Kim Su-Chul
Lee Jong-Cheol
Lee Kwang-Jin
Castellano John A.
Harness & Dickey & Pierce P.L.C.
Rossoshek Helen B
Samsung Electronics Co,. Ltd.
Siek Vuthe
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