Memory re-implementation for field programmable gate arrays

Details Memory re-implementation for field programmable gate arrays Memory re-implementation for field programmable gate arrays

2007-07-31

2007-07-31

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10785608

ABSTRACT:
Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are desirably selected. Based on the outcome of a timing analysis, the most critical signal pin of the selected logic blocks may be identified. Methods of deriving the memory module re-implementation for various types of the most critical pins are disclosed. Procedures are described for integrating physical timing analysis, memory transformation, placement, and routing, as well as for the selection of logic blocks for re-implementation.

REFERENCES:
patent: 6813754 (2004-11-01), Wu et al.
patent: 2005/0204325 (2005-09-01), Fung et al.
patent: 2006/0117280 (2006-06-01), Wallace
patent: 2006/0241921 (2006-10-01), Willis
Suaris et al., “Incremental Physical Resynthesis for Timing Optimization”, Feb. 22, 2004.

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