Memory compiler with ultra low power feature and method of use

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

07137079

ABSTRACT:
The present invention relates to a method of creating a design for a semiconductor memory. In an embodiment, a memory compiler for a semiconductor memory has access to a set of leaf cell designs for use by the memory compiler, the leaf cell designs comprising a power management circuit design as a leaf cell for a memory circuit. A user may elect to allow enablement of an ultra low power feature and the memory compiler creates a design which incorporates the power management circuit in a compiled semiconductor memory macro when the user-selectable option is enabled.

REFERENCES:
patent: 6295627 (2001-09-01), Gowni et al.
patent: 6453448 (2002-09-01), Meyer
patent: 2005/0071693 (2005-03-01), Chun et al.

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