Memory characterization system

Details Memory characterization system Memory characterization system

2000-05-04

2001-06-19

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06249901

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computer aided methods and tools for designing, simulating, and verifying integrated circuit (IC) designs. More specifically, the present invention relates to an efficient and accurate process of characterizing a plurality of instances of a memory compiler circuit.
2. Description of the Prior Art
The design of very large scale integrated (VLSI) circuits using computer aided design (CAD) systems is a very time-consuming and computationally intensive process. As the complexity of VLSI circuit design has increased, a trend has developed wherein VLSI circuit designers incorporate basic circuit building blocks into circuit designs so that the designers no longer start from scratch in designing a chip. This design approach is commonly referred to as an intellectual property (IP) based design approach, and the basic circuit building blocks are referred to as IP blocks.
In accordance with system on a chip (SOC) technology, a variety of circuit building blocks are incorporated onto a single integrated chip, each of the building blocks performing a specific function of an electronic system. The IP building blocks required for a system chip include embedded memory devices such as SRAM, DRAM, ROM, EPROM, and EEPROM type memory devices. It is common for a single SOC to require between 50 and 100 memory devices. Often, more than 50% of the layout area of a system chip is devoted to embedded memory. Because reusability is a key factor in SOC methodology, system chip designers typically reuse a particular embedded memory design throughout a system chip with minor differences between each instance of the memory design such as variations in the size of the memory array of each instance. The selection of a memory instance is typically determined by an IC designer based on system design requirements and the availability of silicon real estate on the system chip. Different configurations of a memory circuit design are also provided. Such configurations include dual port memory and single port memory.
Design layouts for memory circuit IP building blocks are currently available to IC designers from vendors who provide memory layout databases for a memory compiler, or circuit design, different types of memory circuits. A vendor's memory compiler team may generate thousands of memory instances for each type of memory circuit. Memory compiler tools are used to generate a layout and a netlist for each memory circuit design. Components of memory compiler software used by a memory compiler team typically include a circuit design tool, a layout design tool, and a characterization tool.
IC designers require a timing model including a plurality of characterized timing parameters for each memory instance that the IC designer intends to incorporate into a system chip as embedded memory. Important timing parameters include setup time, hold time, memory access time, minimum pulse high and low time, and other I/O pin characteristics. Memory compilers and IC designers are both interested in characterizing and optimizing timing characteristics associated with a memory design.
Memory compiler teams need to generate a timing model by characterizing each of the timing parameters for each memory instance. A timing model for a memory instance may be determined to a certain degree of accuracy by simulating the memory instance. However, simulation of all of the timing characteristics of a memory instance is a very time consuming and computationally intensive process. Because there may be thousands of memory instances for each memory compiler, it is difficult to generate a white box timing model, that is a timing model based on actual simulation results, for each one of the memory instances. A “black box timing model” for a particular instance of a memory design may be estimated using equations and look up tables determined based on timing models determined for other instances of the memory design having a predetermined relationship with the particular memory instance as further explained below. Typically, a memory compiler vendor will generate a white box timing model for “corner” instances of a memory design such as a first instance having a smallest size memory array that is likely to be used by an IC designer, and a second instance having a largest size memory array that is likely to be used in practice. Black box timing models for memory instances having array sizes ranging between those of the first and second characterized instances are typically determined by interpolation techniques or by equations providing estimated timing characteristics. A vendor's memory compiler typically provides the lookup table and/or equations to IC designers for determining the timing characteristics associated with each memory instance. However, the accuracy of typical prior art black box timing models is not consistent. Furthermore, curve fitting is difficult for multi-dimensional variables.
FIG. 1
shows a generalized circuit block diagram of a memory circuit at
10
that may be used for modeling an instance of embedded memory in a system chip. The memory circuit
10
includes: an address decoder
12
having a plurality of address signal inputs
14
for receiving address signals; an array
16
of memory cells
18
arranged in rows and columns, each cell
18
being communicatively coupled with the address decoder
12
via an associated one of a plurality of word lines
20
, which are typically designated by the memory compiler team using convenient names such as WORD_LINE
—
0, WORD_LINE
—
1, . . . WORD_LINE_N, for addressing rows of the array; a sense amplifier
24
responsive to column select address information provided by the address decoder
12
, and being coupled with each of the cells
18
of the array via an associated one of a plurality of lines
26
; a data input buffer
30
having a plurality of ports
32
each being communicatively coupled with one of the bit lines
26
, and having at least one input port
34
for receiving a data input signal designated D
IN
from a source (not shown) that may be provided by another device on the IC chip or provided by an external device via an I/O pin of the chip; and a data output buffer
40
communicatively coupled with the sense amplifier
24
as shown by a line
42
and having at least one output
44
for providing a data output signal designated D
OUT
to processing circuitry (not shown) on the IC chip or to external processing circuitry via an I/O pin of the system chip.
FIG. 2
shows a flow diagram at
70
illustrating a prior art semi-manual process of characterizing timing parameters for a memory instance of a particular memory circuit design which may be modeled generally by the memory circuit
10
(FIG.
1
). The process begins with step
72
in which a memory instance layout data base is generated by a memory compiler team. Note that the process
70
of characterizing timing parameters may be performed by either a memory compiler team, or by an IC designer in which case step
72
may include receiving the memory instance layout database from a vendor. The memory instance comprises a layout database that defines a particular instance memory circuit of a compiler having an array of cells including a plurality of M rows and a plurality of N columns, each cell being defined by a core cell. In step
47
, an IC designer performs a partial layout extraction sub-process including manual estimation and segmenting to generate a netlist. Layout extraction generally refers to a process of converting a layout data base into an extracted electric circuit representation including circuit components such as transistors, resistors, capacitors. etc. The extracted electric circuit representation may then be used for simulating the circuit in order to characterize timing parameters. Note that a memory instance layout database may include millions of geometric objects, and therefore a full scale layout extraction process is computationally intensive, and very time consuming. In order to redu

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