Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-01-25
2005-01-25
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06848090
ABSTRACT:
An abstraction mechanism is disclosed, which is capable of recognizing and abstracting precharged latches and flip-flops, and which is capable of generating a cycle ready representation of the precharged latches and flip-flops. In one embodiment, the abstraction mechanism abstracts precharged latches and flip-flops by using cofactors. In doing so, the abstraction mechanism accesses a logic level representation of a structure. Based upon the logic level representation, the abstraction mechanism derives one or more cofactors. These cofactors are then tested to determine whether they indicate precharge behavior, and whether they indicate latch or flip-flop behavior. If the cofactors indicate both precharge behavior and latch or flip-flop behavior, then the abstraction mechanism abstracts the structure as a precharged latch, or a precharged flip-flop, whichever is appropriate. By recognizing and abstracting precharged latches and flip-flops in this manner, the abstraction mechanism simplifies the functional representation of the structure, and makes it possible to generate a cycle ready representation of the structure.
REFERENCES:
patent: 5657239 (1997-08-01), Grodstein et al.
patent: 6083273 (2000-07-01), Takeuchi
patent: 6442739 (2002-08-01), Palermo et al.
patent: 6539345 (2003-03-01), Jones et al.
patent: 6643829 (2003-11-01), Borkovic et al.
D. T. Blaauw, et al., “Functional Abstraction of Logic Gates for Switch-Level Simulation,” European Conference on Design Automation, pp. 329-333, Feb. 1991.
S. Kundu, “GateMaker: A Transistor to Gate Level Model Extractor for Simulation, Automatic Test Pattern Generation and Verification,” International Test Conference, pp. 372-381, 1998.
R. E. Bryant, “Algorithmic Aspects of Symbolic Switch Network Analysis,” IEEE Transactions on Computer Aided Design, pp. 618-633, Jul. 1987.
R. E. Bryant, “Boolean Analysis of MOS Circuits,” IEEE Transactions on Computer Aided Design, pp. 634-649, Jul. 1987.
R. E. Bryant, “Extraction of Gate Level Models From Transistor Circuits by Four-Valued Symbolic Analysis,” International Conference on Computer Aided Design, pp. 350-353, 1991.
S. Jain, et al., “Automatic Clock Abstraction from Sequential Circuits,” Design Automation Conference, pp. 707-711, 1995.
R. Razden, et al., “Clock Suppression Techniques for Synchronous Circuits,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, pp. 1547-1556, Oct. 1993.
F. Rocheteau, et al., “Tralala: A Fast and Accurate Functional Abstraction Tool For Transistor Netlists,” SAME 99, Accessible from http://www.sansistor.com.
“Statement of Product Sale,” 8 pages, Dec. 1999.
Jain Alok
Reehal Manpreet
Cadence Design Systems Inc.
Garbowski Leigh M.
Hickman Palermo & Truong & Becker LLP
Truong Bobby K.
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