Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-12-22
2010-10-19
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C711S173000
Reexamination Certificate
active
07818701
ABSTRACT:
Disclosed is a method of partitioning a memory, comprising dividing the memory into a first plurality of sub-zones, allocating a plurality of spare blocks in each of the first plurality of sub-zones, resizing the first plurality of sub-zones to a second plurality of sub-zones different from the first plurality, and reallocating the plurality of spare blocks among the second plurality of sub-zones. A circuit for an improved memory controller is described also.
REFERENCES:
patent: 5339400 (1994-08-01), Iijima
patent: 6088777 (2000-07-01), Sorber
patent: 6718430 (2004-04-01), Lin et al.
patent: 6842823 (2005-01-01), Olson
patent: 7149871 (2006-12-01), Conley
patent: 7404060 (2008-07-01), Hoshina
patent: 7529905 (2009-05-01), Sinclair
patent: 7734864 (2010-06-01), Maeda et al.
patent: 2004/0111553 (2004-06-01), Conley
patent: 2005/0005059 (2005-01-01), Tanaka et al.
patent: 2005/0071595 (2005-03-01), Irish et al.
patent: 2006/0206681 (2006-09-01), Suzuki et al.
patent: 2010/0121935 (2010-05-01), Holt
Cypress Semiconductor Corporation
Kik Phallaka
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