Memory tiling architecture

Details Memory tiling architecture Memory tiling architecture

2007-04-17

2007-04-17

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C719S323000, C719S323000, C719S323000

Reexamination Certificate

active

10990237

ABSTRACT:
A method of tiling a customer memory design to configurable memory blocks within a standardized memory matrix. A customer memory capacity and a customer memory width is determined for the customer memory design, and a standardized memory capacity and a standardized memory width is determined for the configurable memory blocks. The customer memory capacity and the customer memory width are selectively transformed by inverse factors based at least in part on a comparison of the customer memory capacity and the standardized memory capacity. Case independent blocks are formed within the configurable memory blocks, where the case independent blocks include gate structures formed in a standardized array in a substrate in which the customer memory design is to be implemented. Case dependent blocks are formed within the configurable memory blocks, where the case dependent blocks are electrically conductive routing layers that selectively connect the case independent blocks according to the transformation of the customer memory design.

REFERENCES:
patent: 6553552 (2003-04-01), Khan et al.
patent: 6678873 (2004-01-01), Kohashi et al.
patent: 6735754 (2004-05-01), Mehrotra et al.
patent: 7013449 (2006-03-01), Schlansker et al.
patent: 2002/0157066 (2002-10-01), Marshall et al.

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