Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-31
2010-12-07
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C324S765010
Reexamination Certificate
active
07849426
ABSTRACT:
The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applied to its gate node and at least one reference device having a zero gate-to-source voltage. A controller is also provided to configure node voltages of the device and/or the reference device to reflect different regions of device operations found in digital and analog circuit applications. Moreover, the controller measures a difference in current between the stress device and the reference device to determine whether NBTI induced threshold degradation has occurred in the stress device. The controller also adjusts an output power supply voltage of the stress device until a performance of the stress device matches a performance of the reference device to account for the NBTI induced threshold degradation.
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Goodnow Kenneth J.
Kemerer Douglas W.
Shuma Stephen G.
Strohacker Oscar C.
Styduhar Mark S.
Chiang Jack
Gibb I.P. Law Firm LLC
International Business Machines - Corporation
LeStrange, Esq Michael J.
Sandoval Patrick
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