Use of non-lithographic shrink techniques for...
Use of overlay diagnostics for enhanced automatic process...
Use of overlay diagnostics for enhanced automatic process...
Use of overlay diagnostics for enhanced automatic process...
Use of redundant routes to increase the yield and...
Use of state nodes for efficient simulation of large digital...
Use of time step information in a design verification system
User defined names for registers in memory banks derived...
User interface for a networked-based mask defect...
User non-volatile memory interface megafunction
User non-volatile memory interface megafunction
User-friendly rule-based system and method for automatically...
Using a partial metal level mask for early test results
Using a reduced cell library for preliminary synthesis to...
Using an embedded processor to implement a finite state machine
Using Boolean expressions to represent shapes within a...
Using budgeted required time during technology mapping
Using constrained scan cells to test integrated circuits
Using constraints in design verification
Using constraints in design verification