Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-09
2005-08-09
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C438S014000, C438S016000, C382S151000
Reexamination Certificate
active
06928628
ABSTRACT:
Disclosed are methods and apparatus for analyzing the quality of overlay targets. In one embodiment, a method of extracting data from an overlay target is disclosed. Initially, image information or one or more intensity signals of the overlay target are provided. An overlay error is obtained from the overlay target by analyzing the image information or the intensity signal(s) of the overlay target. A systematic error metric is also obtained from the overlay target by analyzing the image information or the intensity signal(s) of the overlay target. For example, the systematic error may indicate an asymmetry metric for one or more portions of the overlay target. A noise metric is further obtained from the overlay target by applying a statistical model to the image information or the intensity signal(s) of the overlay target. Noise metric characterizes noise, such as a grainy background, associated with the overlay target. In other embodiments, an overlay and/or stepper analysis procedure is then performed based on the systematic error metric and/or the noise metric, as well as the overlay data.
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Adel Michael E.
Ghinovker Mark
Izikson Pavel
Robinson John
Seligson Joel L.
Beyer Weaver & Thomas LLP.
Garbowski Leigh M.
KLA-Tencor Technologies Corporation
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