Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-08
2009-08-25
Levin, Naum B (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S013000, C703S014000, C703S015000, C703S016000, C703S017000, C703S019000
Reexamination Certificate
active
07581199
ABSTRACT:
An integrated circuit design simulation method is provided that takes advantage of the fact that, when an instance of a circuit module has been simulated under a given set of input conditions, and the resulting output values and delays have been evaluated, another instance of the same module need not be re-simulated when it has the same input combination as the prior circuit module instance. The results computed earlier for the earlier circuit module instance can be re-used for the current circuit module instance.
REFERENCES:
patent: 5163016 (1992-11-01), Har'El et al.
patent: 5481469 (1996-01-01), Brasen et al.
patent: 5550760 (1996-08-01), Razdan et al.
patent: 5666288 (1997-09-01), Jones et al.
patent: 5668732 (1997-09-01), Khouja et al.
patent: 5748486 (1998-05-01), Ashar et al.
patent: 6009256 (1999-12-01), Tseng et al.
patent: 6148436 (2000-11-01), Wohl
patent: 6182268 (2001-01-01), McElvain
patent: 6499129 (2002-12-01), Srinivasan et al.
patent: 6625786 (2003-09-01), Ganesan et al.
patent: 6807520 (2004-10-01), Zhou et al.
patent: 7216307 (2007-05-01), Dastidar et al.
patent: 2003/0036894 (2003-02-01), Lam
patent: 2004/0044510 (2004-03-01), Zolotov et al.
patent: 2004/0078175 (2004-04-01), Shaw et al.
patent: 2006/0074622 (2006-04-01), Scott et al.
Jones; “Accelerating switch-level simulation by function caching”; Design Automation Conference, 1991; 28th ACM/IEEE; Publication Date: 1991; pp. 211-214.
T.-K. Ng et al., “Generation of Layouts from MOS Circuit Schematic: A Graph Theoretic Approach,”22nd Design Automation Conference—IEEE(1985), pp. 39-45.
N.V. Shakhlevich et al., “Adaptive scheduling algorithm based on mixed graph model,”IEEE Proc.—Control Theory Appl., vol. 143, No. 1, Jan. 1996, pp. 9-16.
L.G. Jones et al., “Hierarchical VLSI Design Systems Based on Attribute Grammars,”ACM(1986), pp. 58-69.
K.M. Chandy et al., “Distributed Computation of Graphs: Shortest Path Algorithms,”ACM(1982), pp. 833-837.
P.A. Beerel et al., “Testability of Asynchronous Timed Control Circuits with Delay Assumptions,”28th ACM/IEEE Design Automation Conference—ACM(1991), pp. 446-451.
D. Adler, “Switch-Level Simulation Using Dynamic Graph Algorithms,”IEEE Transactions on Computer-Aided Design, vol. 10, No. 1, Mar. 1991, pp. 346-355.
Dastidar Tathagato Rai
Ray Partha
Yashfe Amir
Dergosits & Noah LLP
Levin Naum B
National Semiconductor Corporation
LandOfFree
Use of state nodes for efficient simulation of large digital... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Use of state nodes for efficient simulation of large digital..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Use of state nodes for efficient simulation of large digital... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4065845